//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

;mainstone.h: Maistone specific defines

; the base address were BLOB is loaded by the first stage loader
BLOB_ABS_BASE_ADDR  EQU   (0xA0000000)

; where do various parts live in RAM
BLOB_RAM_BASE       EQU   (0xA0020000)
KERNEL_RAM_BASE     EQU   (0xA0200000)
PARAM_RAM_BASE      EQU   (0xA01ff000)
RAMDISK_RAM_BASE    EQU   (0xA0400000)

; and where do they live in flash
BLOB_FLASH_BASE		EQU   (0x00000000)
BLOB_FLASH_LEN		EQU   (256 * 1024)
PARAM_FLASH_BASE	EQU   (BLOB_FLASH_BASE + BLOB_FLASH_LEN)
;PARAM_FLASH_LEN	EQU	  (256 * 1024)
PARAM_FLASH_LEN		EQU	  (0)
;KERNEL_FLASH_BASE	EQU   (PARAM_FLASH_BASE + PARAM_FLASH_LEN)
KERNEL_FLASH_BASE	EQU	  (0x40000)
KERNEL_FLASH_LEN	EQU   (1024 * 1024)
RAMDISK_FLASH_BASE	EQU   (KERNEL_FLASH_BASE + KERNEL_FLASH_LEN)
RAMDISK_FLASH_LEN	EQU   (4 * 1024 * 1024)

; the position of the kernel boot parameters
BOOT_PARAMS			EQU	  (0xA01ff000)

; the size (in kbytes) to which the compressed ramdisk expands
RAMDISK_SIZE		EQU   (8 * 1024)


MS_GPSWR_OFFSET		EQU	   0x60

; Table of GPIO output pins which should be set.
GPSR0_VAL	EQU	0x00000000 	;0x00708800    / GPIO [31:0]
GPSR1_VAL	EQU	0x00000380 	;0x03cf0002    / GPIO [63:32]
GPSR2_VAL	EQU	0x00000000 	;0x0021FC00    / GPIO [95:64]
GPSR3_VAL	EQU	0x00110000 	;0x00000000    / GPIO [120:96]

;GPSR3_VAL_LIGHTR (1<<18)
;GPSR3_VAL_LIGHTG (1<<19)
;GPSR3_VAL_LIGHTB (1<<20)

; Table of GPIO output pins which should be cleared.
GPCR0_VAL	EQU	0xffffffff 	;       0x00001000    / GPIO [31:0]
GPCR1_VAL	EQU	0xffffd7ff 	;       0x00000000    / GPIO [63:32]
GPCR2_VAL	EQU	0xffffffff 	;       0x00000000    / GPIO [95:64]
GPCR3_VAL	EQU	0x00Efffff 	;       0x00000000    / GPIO [120:96]

; Table of GPIO pins which should be outputs.
GPDR0_VAL	EQU	0xFFFFFFFF 	;       0xFFFEFC04 ;0xC27B9C04     / GPIO [31:0]
GPDR1_VAL	EQU	0xFFFFFB80 	;       0x00EFAA83    			   / GPIO [63:32]
GPDR2_VAL	EQU	0xEFFFFFFF 	;       0x0E23FC00    			   / GPIO [95:64]
GPDR3_VAL	EQU	0x001fffff 	;       0x01FE1FFF ;0x001E1F81     / GPIO [120:96]

;
; Table of GPIO pin "alternate function" settings. Each pin
; may be "normal" or one of three alternate functions.
;
GAFR0_L_VAL	EQU	0x00000000 ;        0x94F00000    / GPIO [15:0]
GAFR0_U_VAL	EQU	0x00000000 ;        0x015A859A    / GPIO [31:16]
GAFR1_L_VAL	EQU	0x09900000 ;        0x999A955A    / GPIO [47:32]
GAFR1_U_VAL EQU	0x00000000 ;        0x0005A4AA    / GPIO [63:48]
GAFR2_L_VAL	EQU	0x00000000 ;        0x6AA00000    / GPIO [79:64]
GAFR2_U_VAL	EQU	0x00000000 ;        0x55A8041A    / GPIO [95:80]
GAFR3_L_VAL	EQU	0x00000000 ;        0x56AA955A    / GPIO [111:96]
GAFR3_U_VAL	EQU	0x00000000 ;        0x00000001    / GPIO [120:112]

;
; Memory controller setting
;
J3_MSC0_VAL		EQU	0x39F2
K3_MSC0_VAL		EQU 0xA7A3
K18_MSC0_VAL	EQU 0xA7A3
L3_MSC0_VAL		EQU 0x39F2		;Just as J3
L18_MSC0_VAL	EQU 0x39F2

MDREFR_VAL		EQU 0x024C6017 	;0x00000018
MDCNFG_VAL  	EQU 0x0A4C2ACC 	;0x00000AC9
MSC0_VAL		EQU 0x39F2A7A3
MSC1_VAL		EQU 0x0000A691
MSC2_VAL		EQU 0x0000B884
MECR_VAL		EQU 0x00000001
SXCNFG_VAL		EQU 0x40044004
FLYCNFG_VAL		EQU 0x00000000
MCMEM0_VAL		EQU 0x00010204
MCMEM1_VAL		EQU 0x00010204
MCATT0_VAL		EQU 0x00010204
MCATT1_VAL		EQU 0x00010204
MCIO0_VAL		EQU 0x0000C108
MCIO1_VAL		EQU 0x0001C108
MDMRS_VAL		EQU 0x00320032 	;0x00000000

      END
